ON Semiconductor PRIN PACKAGE DEVELOPMENT ENGR _FOL in Suzhou, China

  1. Responsible for Assembly Process Development and Characterization for Code-S and Enabling Technology in Semiconductor FOL (Front of Line) area as Process Development Engineer

  2. Major Process Responsibility on Die Attach (Soft Solder and Ag Epoxy) ,Wire Bonding (Heavy Al Wire Bonidng), SMT and support heatsink attach process.

  3. Capable to understand and discuss proposed design and new proposal upgraded

  4. Capability understanding Design FMEA, upgrading DFMEA and making Process FMEA from DFMEA

  5. Capability to define KPIV from FMEA Failures Modes

  6. Capability to define KPOV and making result of KOPV and analysis from it

  7. Responsible for providing Technical reports with satisfying KPIV versus KPOV from FMEA failures modes based on JMP analysis

  8. Working with development engineers to generate and create documents deliverables such as preliminary Control Plan from D/PFMEA according to APQP procedure

  9. Responsible for Sharing and Communication with Development Engineers and Manufacturing Engineers

  10. Pro typing Line Sample Building and Line Equipments Maintenance & Management

  11. Capable for Equipment and Tooling Set-up

  12. Responsible for Tool and JIG design understanding working with designers and vendors for new development tool designs (Die Attach Tooling, Al & Au wire bonding clamp design, other jig design)

  13. Responsible for readiness of tools and Jigs meeting target schedule without EON owner’s schedule impacts to generate proper outputs within schedule

  14. Responsible to meet EON cycle time on Technology Development

  15. Leading Proto Typing Line Operators to do right job

  16. Sharing technical issues and new result to related EON owners and manufacturing engineering team

  17. Technical Leadership on Assembly Process

  18. Capable to initiate new Process and new Equipment working with development engineers and vendors

  19. Responsible for PO Spec. generation and Buy-off

  20. Capable to create COO for Process and Equipment Comparison

  21. Capable for Benchmarking New and Better Process and Equipments that does not exist in company

  22. Capability to create Assembly Technology Roadmap

  23. Capability to generate Characterization and out of design Rule by Co-work with Dev. Engineer and NPI Process engineers

  24. Capable to understand customer requirements, application, EHS and design

  25. Capable to find technical and systematic solution and schedule for failures of process, reliability, quality, manufacturability, cost, and cycle time that are related with process

  26. Supporting Production Related Quality Issues for Manufacturing

  27. Leading the Pre-work and supporting Code-S with NPI Process Engineers

  28. To share and update project progress, risk of delay, constraints by weekly report and update technical Web site and report to manager

  • Experienced years : Longer than 8 to 10years in Die attach and Wire bonding

  • Experienced areas : Soft Solder Die Attach (ESEC), Al wire bonding (K&S, Choonpa), SMT

  • Experienced jobs : Semiconductor Assembly Process Development, Equipment and Tooling set-up, process/equipment/material troubleshooting and control, Purchase spec/selection, Qualification for equipment and material, Experience of consulting on Leadframe design, Soft Solder and Ag Epoxy bondingclamp design, Al wire bonding clamp

  • Experienced packages: Semiconductor Packages. Highly Preferred Power discrete (like TO220, D-Pak, D2PAK) and Power module packages (like SPM, IPM, IGBT/Diode module)

  • Nationality : Chinese

  • Education: master's degree material science with proven record in new process introduction

  • Skills: Communication skills, written English and speaking with multi-cultural foreign engineers, JMP & Data analysis. Skilled Excel Spreadsheet and Power Point Presentation.

  • Other characteristics such as personal characteristics : Self motivated, independent, open mind to communicate, be willing to take risk and managing

Job: Engineering


Location: CN-CN-Suzhou

Requisition ID: 1705832

ON Semiconductor is an Equal Employment Opportunity Employer and prohibits discrimination on the basis of age, race, color, religion, gender, sexual orientation, national origin, citizenship, protected veteran status, disability status, or any other federal, state or local protected classes. ON is committed to providing equal employment opportunity to qualified individuals, regardless of protect class status.