ON Semiconductor Senior IC Layout Designer in Milan, Italy
ON Semiconductor’s Cloud Power group is hiring a senior IC layout engineer with direct experience in creating layouts for power management products. The candidate will be asked to work on a wide assortment of products from big analog/little digital to complete SOC developments. The successful candidate will be responsible for IC layout for analog and digital circuits at .18u and below technology nodes, able to be a top level layout lead as well as work on blocks when required, and able to bring layouts to the LVS/DRC/ERC clean state within the committed schedule. The candidate must be able to work in a small “startup-like” team environment with a global team. Analytical approach to problem solving is highly required.
Analog, power and mixed signal IC layout design
Top level floor planning for the complete chip
Block level design and floor planning
Perform all DRC/LVS/ERC and other automated checks to ensure IC reliability and manufacturability per all process design rules
Participation in team meetings, problem solving sessions and other team discussions as required.
Work diligently to accomplish project goals and meet project schedule
Work with both US and Europe locations for project development
Interface with analog design, digital design and back end design, CAD, ESD, verification, and process engineers as needed to successfully bring new designs to tape out.
Written and oral communication with the development team regarding floor planning reviews, layout reviews, all deliverables, project updates and issues
Associates degree or Technical certificate with 10 years (or BSEE with 8 years) of relevant industry experience. Exceptional talent may be credited towards education and experience requirements
Familiar with Silicon process technology
Experience with layout of power management circuits like DC/DC regulators, Drivers, LDOs, Band gaps voltage references, etc.
Experience with SOC layout
Experience and understanding of analog matching techniques, power device layout techniques, electro-migration prevention techniques, guard-ring design for latch-up prevention, noise coupling reduction techniques and ESD protection layout techniques
Proven track record of released power management products- Must be able to work independently with limited supervision. Must be very organized, self motivated and passionate about the work
Tools: Cadence Design Tools proficiency required; LVS, DRC, ERC, CALIBRE(and similar parasitic extraction tools). Digital circuit layout generation tools experience desired. Package assembly rule check tools experience desired
Excellent verbal and written communication skills
Knowledgeable in Skill coding and proficient use of autorouting tools a plus
Title: Senior IC Layout Designer
Requisition ID: 1801197
ON Semiconductor is an Equal Employment Opportunity Employer and prohibits discrimination on the basis of age, race, color, religion, gender, sexual orientation, national origin, citizenship, protected veteran status, disability status, or any other federal, state or local protected classes. ON is committed to providing equal employment opportunity to qualified individuals, regardless of protect class status.